Many complex circuits use boundary scan testing techniques to test the output buffers of the circuit. For circuits using conventional two-state or three-state CMOS output buffers, designers commonly use the boundary scan implementation defined in the IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1-1990 and IEEE Std 1149.1a-1993 (referred to herein as the IEEE 1149.1 Specification or Standard), which is incorporated herein by reference. As is well known, a boundary scan implementation allows for testing of interconnects in a board environment by loading or "scanning in" test patterns into a series of interconnected boundary scan registers (BSRs). Each test pattern loaded in the BSRs provides a different set of control and data signals to the output drivers. The responses of the output drivers to the test patterns can be captured by an adjacent circuit on the board and scanned out. To run a functional test vector, an input test pattern is scanned in through the BSRs. After one or more clock cycles, the response of the circuit can then be captured in the BSRs and either scanned out or monitored at the output pads.
FIG. 1 is a circuit diagram of a portion of a circuit 100 using a conventional boundary scan implementation for I/O drivers that have three-state drivers (TSDs). The circuit 100 includes a conventional TSD 102 serving as an output driver, having an output lead connected to an I/O pad 104. The I/O pad 104 is also connected to an input lead of an input driver 105, which drives any signal received from the I/O pad 104 to other portions (not shown) of the circuit 100 in the conventional manner. The circuit 100 also includes conventional BSRs 106 and 107, which are interconnected to form part of a "scan chain" for loading test patterns and scanning out capture data. The BSR 106 includes a capture, shift and update stage (CSUS) 108 that has an output lead connected to an input lead 111 of a two-input multiplexer 112. The other input lead 113 of the multiplexer 112 is connected to receive a fcn.sub.-- oe signal provided by another portion (not shown) of the circuit 100. The multiplexer 112 has an output lead 114 connected to the output enable lead of the TSD 102.
Similarly, the CSUS 110 has an output lead connected to an input lead 115 of another two-input multiplexer 116. The other input lead 117 of the multiplexer 116 is connected to receive a fcn.sub.-- data signal provided by another portion (not shown) of the circuit 100. The multiplexer 116 has an output lead 118 connected to an input lead of the TSD 102.
In operation during the boundary scan mode, the CSUSs 108 and 110 are loaded with a test pattern in the conventional manner (see the aforementioned 1149.1 specification). The test pattern is predetermined so that the CSUS 108 is loaded with a value for enabling or disabling the TSD 102, as desired. Thus, the CSUS 108 provides a bsr.sub.-- oe signal to the multiplexer 112. Similarly, the CSUS 110 is loaded with a desired value for the data signal to be provided to the input lead of the TSD 102. Thus, the CSUS 110 provides a bsr.sub.-- data signal to the multiplexer 116. The multiplexers 112 and 116 receive a mode signal via a line 120 that causes the multiplexers 112 and 116 to select the bsr.sub.-- oe and bsr.sub.-- data signals. A test access port (TAP) controller according to the 1149.1 specification typically provides this mode signal. Accordingly, the TSD 102 is controlled as desired by the test pattern loaded into the BSRs to test one of the various functions of the I/O driver. The output signal provided by the TSD 102 could then be monitored at the I/O pad 104 and compared to the expected result. Other test patterns may then be loaded to test other functions of the I/O drivers.
To test the input portion of the I/O driver, a test signal can be externally provided to the I/O pad 104. The driver 106 then drives the test signal to the rest of the circuit 100 (not shown). The response of the circuit 100 can then be captured in the BSRs. The capture data can then be scanned out from the BSRs and compared to the expected response. In this example, the CSUS 108 and 110 receive capture data through input leads 122 and 124, respectively.
During the functional mode, the mode signal is configured to cause the multiplexers 112 and 116 to select the fcn.sub.-- oe signal and the fcn.sub.-- data signal instead of the bsr.sub.-- oe and bsr.sub.-- data signals. Of course, the fcn.sub.-- oe and fcn.sub.-- data signals are generated by the circuit 100 during normal functional operation. Consequently, the multiplexers 112 and 116 provide the fcn.sub.-- oe and fcn.sub.-- data signals to serve as the data and oe signals received by the TSD 102.
However, some high performance circuits such as, for example, microprocessors, have to use other types of drivers for improved performance. One type that can be used is a linearized impedance control type (LIC) driver. FIG. 2 is a circuit diagram of an example of a portion of a circuit 200 including a LIC driver 202. Note, like reference numbers are used throughout the drawings for elements that has substantially similar structure and function. The LIC driver 202 includes a pull-up unit 204 and a pull-down unit 206. The pull-up unit 204 is connected to receive a q.sub.-- up signal via an input lead 208. Similarly, the pull-down unit 206 is connected to receive a q.sub.-- dn signal via an input lead 210. The LIC 200 can provide the functionality (i.e., a logic zero, logic one and high impedance state) of a conventional CMOS TSD through appropriate control of the logic levels of the q.sub.-- up and q.sub.-- dn signals, as summarized in Table 1 below.
TABLE 1 ______________________________________ q.sub.-- up q.sub.-- dn LIC out ______________________________________ 0 0 0 0 1 Z 1 0 Illegal 1 1 1 ______________________________________
The "Z" in Table 1 indicates a high impedance state. As is well known in the art of LIC drivers, the q.sub.-- up and q.sub.-- dn signals must be generated so that the q.sub.-- up signal is not at a logic one level at the same time the q.sub.-- dn signal is at a logic zero level.
It is appreciated that the q.sub.-- up and q.sub.-- dn signals of the LIC driver are not equivalent to the data and oe signals of a conventional CMOS TSD. That is, the oe and data signals cannot simply be replaced by the q.sub.-- up (or q.sub.-- dn) signals in an I/O driver using a LIC driver. Thus, circuits using boundary scan implementations according to the IEEE 1149.1 specification cannot be used with circuits having LIC drivers. However, because the IEEE 1149.1 standard is widely used in the industry, there is a need for a system that allows LIC drivers to be used with boundary scan implementations according to the IEEE 1149.1 specification.